This invention relates to programmable logic devices. More particularly, this invention relates to a field programmable gate array (FPGA) employing, e.g., antifuses, with an embedded configurable computational unit.
A programmable logic device is a versatile integrated circuit chip, the internal circuitry of which may be configured by an individual user to realize a user-specific circuit. To configure a programmable logic device, the user configures an on-chip interconnect structure so that selected input terminals and selected output terminals of selected on-chip circuit components are electrically connected together in such a way that the resulting circuit is the user-specific circuit desired by the user. Programmable logic devices employ between selected wire segments, e.g., amorphous silicon antifuses that are xe2x80x9cprogrammedxe2x80x9d to connect the selected wire segments together electrically. Which antifuses are programmed and which antifuses are left unprogrammed determines how the circuit components are interconnected and therefore determines the resulting circuit.
A field programmable gate array (an xe2x80x9cFPGAxe2x80x9d) is one type of programmable logic device. For background information on field programmable gate arrays employing antifuses, see: xe2x80x9cField Programmable Gate Array Technologyxe2x80x9d edited by Stephen Trimberger, 1994, pages 1-14 and 98-170; xe2x80x9cField-Programmable Gate Arraysxe2x80x9d by Stephen Brown et al., 1992, pages 1-43 and 88-202; xe2x80x9cPractical Design Using Programmable Logicxe2x80x9d by David Pellerin and Michael Holley, 1991, pages 84-98; the 1995 QuickLogic Data Book, 1995, pages 1-5 through 2-11 and 6-3 through 6-18; the 1995 Actel FPGA Data Book And Design Guide, 1995, pages ix-xv, 1-5 through 1-34, 1-51 through 1-101, 1-153 through 1-222, 3-1 through 4-56; U.S. Pat. No. 5,424,655 entitled xe2x80x9cProgrammable Application Specific Integrated Circuit Employing Antifuses and Methods Thereforxe2x80x9d; U.S. Pat. No. 5,825,201 entitled xe2x80x9cProgramming Architecture for a Programmable Integrated Circuit Employing Antifuses.xe2x80x9d The contents of these documents are incorporated herein by reference.
A plurality of configurable computational units is embedded in a programmable device, such as a field programmable gate array, in accordance with the present invention. Each configurable computational unit includes an adder circuit that is switchably coupled to a multiplier circuit and an accumulator circuit via, e.g., multiplexers. The configurable computational unit may be configured permanently or on the fly to perform desired arithmetic type functions efficiently and effectively. For example, the computational unit may be configured for digital signal processing functions, filtering functions, and algorithm functions. The computational units may be cascaded by programmably connecting the computational units together, e.g., through the routing resources of the programmable device.